1. Field of the Invention
The present invention relates to a method of forming a pattern of doped regions, and more particularly, to a method of forming a pattern of doped regions on a mask.
2. Description of the Prior Art
With the trend of miniaturization of the electronic products and peripherals, research about thin structures and high integration of the semiconductor devices have become the essential subjects and developing aspects in the industry, and the lithography technology plays an important role to determine the performances of the semiconductor devices.
In semiconductor manufacturing processes, the integrated circuit layout is first designed and formed as a mask pattern. The mask pattern is then proportionally transferred to a photoresist layer disposed on the semiconductor wafer through an exposure process followed by a development process. Subsequently, a corresponding etching process is performed in order to manufacture the semiconductor devices on the semiconductor wafer. Furthermore, a photoresist layer may serve as a mask when an ion implantation process is performed to form lightly doped drain (LDD) regions or doped source/drain regions of the MOS transistor in the semiconductor wafer.
However, during the ion implantation process, the amount of dopant received by the semiconductor wafer may be affected by the formed pre-layer structures and cause micro-loading effects. In other words, since the pre-layer structures are randomly distributed over the semiconductor wafer, after the ion implantation process, the amount of dopant per unit area received by the semiconductor wafer totally exposed will be larger than the amount of dopant per unit area received by the semiconductor wafer partially covered by the pre-layer structures. Therefore, the formed doped regions across the pre-layer structures may suffer unexpected defects such as twists or deformations, which may lower the process yield and the process window. Consequently, how to improve the completeness of the doped regions neighboring the pre-layer structures to increase the efficiency of the semiconductor device, is still an important issue in the field.